Overcurrent Fault Detection Device for Electrical Drive Control System

ABSTRACT

An overcurrent fault detection device includes: an inverter converting DC current to three-phase AC currents for driving a motor; a DC voltage detector; phase current detectors; a rotational position detector that detects a rotational angle of the motor; a control circuit that controls a gate drive circuit, which controls the inverter at every predetermined cycle, based upon the phase current values, a motor rotational angle detection value, and a speed command or a torque command from a higher-order control device; and a decision-making circuit that detects an overcurrent based upon the phase current values at every predetermined cycle, wherein: the decision-making circuit determines whether or not the phase current values exceed a predetermined amplitude threshold value by frequency detection for any of the phase current values exceeding the predetermined amplitude threshold value, and determines that an overcurrent has occurred upon detecting the frequency.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. application Ser. No.13/213,274, filed Aug. 19, 2011, which claims priority under 35 U.S.C.§119 from Japanese Patent Application No. 2010-194067, filed Aug. 31,2010, the entire disclosures of which are expressly incorporated byreference herein.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a device that detects an overcurrentattributable to a short-circuit abnormality occurring in an electricaldrive control system and a detection method adopted in the device.

2. Description of Related Art

An electrical drive control system of a hybrid electric vehicle or anelectric vehicle achieves variable-speed drive of an AC motor byutilizing a power conversion device constituted with a voltage inverter(referred to simply as an “inverter” in the following description of theinvention) which converts a DC voltage to an AC voltage. Such aninverter is equipped with a fault detection circuit for detecting, forinstance, an overcurrent.

If, for instance, an output ground fault attributable to electricallyconductive foreign matter, or line-to-line short-circuit orphase-to-phase short-circuit attributable to a dielectric breakdownoccurring inside the motor connected to the electrical drive controlsystem occurs on the output side of the inverter in the electrical drivecontrol system, the amplitude of a current output from the inverter willincrease quickly, and an overcurrent state comes up in the electricaldrive control system, in which a current exceeding the maximum ratedcontinuous current or the short-time rated current of the transistorsconstituting the inverter flows.

The inverter disclosed in Japanese Laid Open Patent Publication No. S61-98188 determines that an overcurrent has occurred upon detecting acurrent exceeding a predetermined threshold value.

SUMMARY OF THE INVENTION

When the inverter and its peripheral circuits are in a fault mode, suchas any of those in (1) to (3) below, an overcurrent in the inverteroutput may be caused by LCR resonance assuming a frequency in a range ofseveral kHz through a frequency exceeding 100 kHz and in such a case,the inverter may output an electric current that includes an oscillatingcurrent attributable to the resonance superposed on the current(low-frequency current) corresponding to a command current.

(1) Output ground fault/top fault

(2) Output line-to-line short-circuit

(3) Output phase-to-phase short-circuit

An oscillating current with a high frequency occurring in the faultmodes (1) to (3) cannot be accurately detected through the processingdisclosed in patent literature 1 executed by the microcomputer bysampling the current value with a sampling cycle of approximately 10kHz. In addition, it may also be difficult to accurately detect anovercurrent even with a comparator and a method as disclosed in JapaneseLaid Open Patent Publication No. S 61-98188, in which it is determinedthat an overcurrent has occurred if the current amplitude exceeds apredetermined threshold value.

According to the 1st aspect of the present invention, an overcurrentfault detection device, comprises: an inverter that converts a DCcurrent to three-phase AC currents in order to drive a motor; a DCvoltage detector that detects a DC voltage value of a DC voltage flowingto the inverter; phase current detectors that detect respective phasecurrent values of the three-phase AC currents; a rotational positiondetector that detects a rotational angle of the motor; a control circuitthat controls a gate drive circuit, which controls output currents ofthe inverter at every predetermined cycle, based upon the phase currentvalues provided by the phase current detectors, a motor rotational angledetection value provided by the rotational position detector and a speedcommand or a torque command issued by a higher-order control device; anda first decision-making circuit that detects an overcurrent based uponthe phase current values detected by the phase current detectors atevery predetermined cycle, wherein: the first decision-making circuitdetermines whether or not the phase current values exceed apredetermined amplitude threshold value by carrying out frequencydetection for any of the phase current values exceeding thepredetermined amplitude threshold value, and determines that anovercurrent has occurred upon detecting the frequency.

According to the 2nd aspect of the present invention, an overcurrentfault detection device according to the 1st aspect, further comprises: asecond decision-making circuit that detects an overcurrent in the everypredetermined cycle, wherein: the second decision-making circuitdetermines that an overcurrent has occurred if any of the phase currentvalues detected by the phase current detectors exceeds a predeterminedamplitude threshold value.

According to the 3rd aspect of the present invention, in an overcurrentfault detection device according to the 1st aspect, it is preferred thatthe first decision-making circuit includes a comparator with hysteresisprovided with a predetermined hysteresis width, which carries out thefrequency detection for any of the phase current values.

According to the 4th aspect of the present invention, in an overcurrentfault detection device according to the 3rd aspect, it is preferred thatthe first decision-making circuit further includes a hysteresis centralvalue altering circuit that adjusts a hysteresis center assumed by thecomparator with hysteresis in correspondence to a predetermined currentvalue.

According to the 5th aspect of the present invention, in an overcurrentfault detection device according to the 3rd aspect, it is preferred thatthe first decision-making circuit further includes a subtractor circuitthat subtracts a predetermined current value from any of the phasecurrent values and inputs subtraction results; and an output from thesubtractor circuit is input to the comparator with hysteresis.

According to the 6th aspect of the present invention, in an overcurrentfault detection device according to the 4th or 5th aspect, it ispreferred that the first decision-making circuit further includes asample hold; and any of the phase current values held by the sample holdat a predetermined time interval is used as the predetermined currentvalue.

According to the 7th aspect of the present invention, in an overcurrentfault detection device according to the 4th or 5th aspect, it ispreferred that a command current value is used as the predeterminedcurrent value.

According to the 8th aspect of the present invention, an overcurrentfault detection device according to any one of the 3rd through 7thaspects, further comprises: counters that count numbers of times ofexceeding a predetermined amplitude for the phase current valuesrespectively, by counting changes in output from the comparator withhysteresis, wherein: the first decision-making circuit determines thatan overcurrent has occurred upon detecting that any of the phase currentvalues takes on a frequency of which amplitude exceeds a predeterminedamplitude, based upon a count value having been counted on the counters.

According to the 9th aspect of the present invention, an overcurrentfault detection device according to any one of the 3rd through 7thaspects, further comprises: a capture that detects a rising edgeposition and a falling edge position of a pulse output from thecomparator with hysteresis; and a free-run counter, wherein: the firstdecision-making circuit detects that a cycle length of any of the phasecurrent values exceeding a predetermined amplitude based upon the risingedge position and the falling edge position of the pulse, and detects afrequency of any of the phase current values exceeding the predeterminedamplitude based upon the cycle length.

According to the 10th aspect of the present invention, in an overcurrentfault detection device according to any one of the 1st and 3rd through9th aspects, it is preferred that a cause of an overcurrent faultoccurring in an electrical drive control system is determined, basedupon a frequency of any of the phase current values exceeding thepredetermined amplitude, which is detected by the first decision-makingcircuit.

According to the 11th aspect of the present invention, in an overcurrentfault detection device according to any one of the 1st through 10thaspects, it is preferred that gate signals for transistors at theinverter are turned off so as to protect the transistors upondetermining that an overcurrent has occurred.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram showing the overall structure of the electricaldrive control system achieved in an embodiment of the present invention,which includes a control circuit equipped with the overcurrent faultdetection device according to the present invention.

FIGS. 2A to 2C each present an example of an inverter current detectioncircuit that may be used in a gate protection circuit.

FIG. 3 is a block diagram presenting an example of a structure that maybe adopted in the control circuit built into an electrical drive controlsystem embodying the present invention.

FIG. 4 presents a flowchart of microcomputer processing that may beexecuted for purposes of current control in the electrical drive controlsystem.

FIG. 5 presents a flowchart of microcomputer processing that may beexecuted for overcurrent fault detection in the prior art.

FIGS. 6A through 6D are circuit diagrams respectively showing how aground fault, a power short-circuit, line-to-line short-circuit andphase-to-phase short-circuit may occur in the electrical drive controlsystem.

FIGS. 7A through 7C are circuit diagrams showing a ground faultequivalent circuit and the current path through which the electriccurrent will travel in the event of a ground fault in the electricaldrive control system.

FIGS. 8A and 8B are circuit diagrams showing the current path throughwhich the electric current will travel in the event of line-to-lineshort-circuit in the electrical drive control system.

FIG. 9 schematically shows how the current control in the electricaldrive control system may enter an oscillating state.

FIG. 10 presents an example of a current waveform in an oscillatingstate as sampled by the microcomputer.

FIG. 11 presents a flowchart of the overcurrent fault detectionprocessing according to the present invention executed by the controlcircuit shown in FIG. 3.

FIG. 12 is a block diagram presenting another example of a structurethat may be adopted in the control circuit built into an electricaldrive control system embodying the present invention.

FIGS. 13A and 13B respectively show the capture operation executed bythe control circuit shown in FIG. 12 and the capture data stored intothe RAM through a DMA transfer.

FIG. 14 presents a flowchart of the overcurrent fault detectionprocessing according to the present invention executed by the controlcircuit shown in FIG. 12.

FIG. 15 schematically illustrates the overcurrent fault detection deviceand the overcurrent fault detection method according to the presentinvention in a functional block diagram.

FIGS. 16A through 16C show circuit structures that may be adopted invarious comparators with hysteresis.

FIG. 17 presents an example of a current waveform of a current enteringan oscillating state in the event of phase-to-phase short-circuit.

FIG. 18 presents an example of a circuit that may be built into the gatedrive circuit in order to achieve overcurrent protection by hardware.

FIG. 19 presents a flowchart of determining process for the cause ofovercurrent according to the present invention.

DESCRIPTION OF PREFERRED EMBODIMENTS

Before describing embodiments of the present invention in reference tothe drawings, the overall operations of an electrical drive controlsystem that includes a control circuit equipped with the overcurrentfault detection device according to the present invention, an invertercircuit and a motor and how an overcurrent may occur due to a fault inthe electrical drive control system are explained so as to clearlyhighlight the object of the present invention.

Operations of the Electrical Drive Control System and how an OvercurrentOccurs

FIG. 1 is a schematic diagram showing the overall structure of theelectrical drive control system. The electrical drive control systemcomprises a battery 1, an inverter 2, an AC motor 3, a DC input voltagedetector 4, a U-phase current detector 5, a V-phase current detector 6,a W-phase current detector 7, a rotational angle detector 8, a controlcircuit 9, a gate drive circuit 10 and a power source 11 that providespower needed for control and gate drive. Upon receiving a speed commandor a torque command, issued by an external higher-order control devicebased upon vehicle driver actions and vehicle conditions, the electricaldrive control system controls the gate drive circuit for controlling theU-phase, V-phase, and W-phase currents being supplied from the invertercircuit 2 to the motor so as to generate a rotational torque needed bythe motor 3 based upon a DC voltage value vdc provided by the DC voltagedetector 4, a U-phase current value iu, a V-phase current value iv and aW-phase current value iw respectively provided by the current detectors5, 6 and 7 and the rotational position angle indicating the rotationalposition of the motor rotor provided by the rotational position detector8.

It is to be noted that the DC voltage value vdc, the phase currentvalues iu, iv and iw and the rotational position angle mentioned aboveare each output actually as a voltage of, for instance, 0 to 5V from thecorresponding detector and input to the control circuit 9. In addition,in the following explanation of the operations of the control circuit 9,the DC voltage value vdc, the phase current values iu, iv and iw, therotational position angle and other current values and voltage valuesinput to the control circuit 9 are all referred to as correspondingvoltage values of 0 to 5V. Furthermore, the subsequent explanation ofthe processing executed by the microcomputer included in the controlcircuit is provided by assuming that these values are digital valuesachieved through A/D conversion of the corresponding 0 to 5V voltages.As long as there is no risk of misunderstanding, a current value and avoltage value may be simply referred to as a current and a voltagerespectively.

While the high-power transistors (Tu+, Tu−, Tv+, Tv−, Tw+, Tw− inFIG. 1) used in the inverter 2 can be continuously operated at 300 [A](collector temperature TC=25° C.) in a case of continuous operation (DCoperation), a twice as much power, i.e., up to 600 [A], can be suppliedin a case of pulsed operation.

Since the high-power transistors used in the inverter are expensive,various protective measures are normally taken by controlling them via amicrocomputer. In addition, a current control device is often mounted ina drive source that drives a primary motor in automotive applications.Accordingly, any overcurrent state that may occur in the inverter, too,is detected through sampling and necessary actions are taken throughprocessing executed by the microcomputer as part of the microcomputercontrol cycle.

In addition, the inverter gate drive circuit assumes a protectivefunction whereby a gate signal is turned off in reference to apredetermined current threshold value (e.g., 600 [A]) so as to ensurethat the inverter is protected with a high degree of reliability.Regarding detection of the current, in place of the current detected inthe high power transistors for controlling these, the current may bedetected via a shunt resistor disposed in a line located on the negativeside of the DC power source, as shown in FIG. 2A, or, when the maincurrent exceeds several hundred Amperes, the current subdivided withmulti-emitters in the transistor from the main current may be detectedvia a shunt resistor, as shown in FIG. 2B, or as an alternative, acollector—emitter voltage at the transistor may be detected and the maincurrent may be indirectly detected based upon the saturation voltagecharacteristics corresponding to the collector current detected when thetransistor is in the ON state, as shown in FIG. 2C. The detection valuefrom any of these detection methods is compared with a predeterminedlevel by a comparator and, depending upon the comparison results, thetransistor gate may be turned off.

As shown in FIG. 1, the inverter 2 is constituted with three arms. Eacharm is normally made up with two transistors and two diodes, with thecollector and the emitter of one transistor respectively connected tothe positive side of the battery and the collector of the othertransistor. The emitter of the other transistor is grounded on thenegative side of the battery. The two diodes are each connected to oneof the two transistors, so that the anode and the cathode of each diodeare respectively connected in parallel to the emitter and the collectorof the corresponding transistor.

The two transistors in each arm enter the ON state mutually exclusivelywith an off-to-on switchover completed with a delay in order to preventa short-circuit of the positive and negative power lines from occurringduring a time lag elapsing while a transistor enters the OFF state. Itis assumed that the processing described above is executed based uponthe PWM output signals mentioned in the following description of thepresent invention.

A C0 capacitor 12 (hereafter referred to as a main capacitor), whichabsorbs a current ripple occurring at a switchover, and a C1 capacitor13 and a C2 capacitor 14 provided for noise removal, are all connectedto the DC input side of the inverter 2. The C0 capacitor 12 andin-series connected capacitors C1 capacitor 13, C2 capacitor 14(hereafter, the C1 capacitor and the C2 capacitor may be collectivelyreferred to as a Y capacitor) are connected in parallel between apositive terminal and a negative terminal of the battery. A serialconnection point K, at which the C1 capacitor 13 and the C2 capacitor 14are connected in series, is grounded to the chassis or the like.

The motor 3 includes a stator with three-phase windings disposed at thecore thereof. Ends of each phase windings, located on one side, areconnected to one another through a Y connection, whereas the other endsof the phase windings are each connected to a connection point at whichthe emitter of one transistor is connected with the collector of theother transistor in one of the arms constituting the inverter 2. Inaddition, the motor further includes a rotor that rotates with aspecific gap from the stator. While a detailed description is notprovided, a rotor in an induction motor includes a secondary winding,whereas a rotor in a synchronous motor includes permanent magnets. Ineither case, a torque is generated with the electromagnetic forceoccurring between the rotor and the stator by the currents flowingthrough the stator windings. The AC output current, i.e., the motorwinding current, and the rotor angle position are detected forcontrolling the output current from the inverter 2 via the controlcircuit 9, so that a U-phase current, the V-phase current and a W-phasecurrent are supplied imparting a predetermined level of drive force.

While the description above is given by assuming that the invertersupplies a current used to drive the motor, the inverter provideselectric currents to be stored into the battery when the vehicle is in adecelerating state and the motor is utilized as a generator (duringenergy regeneration). While power is stored into the battery undercontrol executed by another control circuit (not shown) that controlsbattery charge/discharge, an explanation of the battery charge/dischargecontrol is omitted.

FIG. 3 is a block diagram presenting an example of a structure that maybe adopted in the control circuit 9 in an embodiment of the presentinvention. This control circuit 9 has a built-in overcurrent protectionfunction whereby the control circuit determines that an error hasoccurred if the amplitudes of a phase current value and the DC voltagevalue exceed a predetermined value and has the gate drive circuit turnoff the gate signals for the inverter transistors so as to protect thetransistors.

A microcomputer 39 constituting the core of the control circuit 9 inFIG. 3 is built into the control circuit shown in FIG. 1. The outputs(phase current values) from the various phase current detectors areinput to a comparator with hysteresis 20 and are also input to an A/Dconverter 19 in the microcomputer 39 via a multiplexer & sample hold 32(sampling circuit). In addition, the output (DC voltage value) from theDC voltage detector 4 is input to the A/D converter in the microcomputer39 via the multiplexer & sample hold 32.

The microcomputer 39 cyclically executes inverter current control andalso executes overcurrent protection processing upon determining that anerror has occurred whenever the amplitude of a phase current valueexceeds a predetermined value as detailed later by sampling the phasecurrent values and the DC voltage value via the multiplexer & samplehold 32.

The microcomputer 39 in the control circuit 9 controlling the outputcurrents as described above may execute the control processing as shownin the flowchart presented in FIG. 4. This processing should be executedover every carrier cycle of the inverter pulse width modulation(hereafter referred to as “PWM”).

The following is a description of the inverter current control executedin the embodiment of the present invention, given in reference to FIG.4. Following the processing start, a d-axis current command id* and aq-axis current command iq*, having been calculated and stored throughseparate processing, are read from the memory in step S801. In step S802and step S803, the A/D conversion results of the three-phase outputcurrents iu, iv and iw (see FIG. 1) and the DC voltage vdc arerespectively read from specific registers. Then, in step S804, therotational angle θ is read from an RD converter connected to an externalmemory data bus 25 of the microcomputer 39.

In step S805, the overcurrent protection processing, which is to bedescribed later, is called up. Subsequently, upon returning to thecontrol processing flow, the operation proceeds to step S806. In stepS806, d-axis and q-axis currents (id, iq) are calculated through d-qcoordinate conversion executed based upon the 3-phase currents (iu, ivand iw) and the rotational angle θ having been read. Next, in step S807,the actual currents are subtracted from the d-axis command current andthe q-axis command current so as to calculate current deviations (ed,eq). In step S808, a d-axis voltage command and a q-axis voltage commandare calculated by executing PI arithmetic operation processing asexpressed in expression (1) below individually on the d-axis currentdeviation and the q-axis current deviation.

vd=Kpd·ed+Kid{ed+ed0}

vq=Kpq·eq+Kiq{eq+eq0}  (1)

In the expressions above, Kpd and Kpq respectively indicate a d-axisproportional gain and a q-axis proportional gain, and Kid and Kiqrespectively indicate a d-axis integral gain and a q-axis integral gain.In addition, ed and eq represent the d-axis current deviation and theq-axis current deviation respectively, whereas ed0 and eq0 respectivelyindicate the d-axis current deviation and the q-axis current deviationhaving been determined in the immediately preceding sampling cycle(i.e., when the processing in the flowchart was executed for theprevious cycle).

In step S809, the current deviations (ed, eq) are stored as the mostrecent sample values (ed0, eq0). In step S810, the d-axis and q-axisvoltage commands (vd, vq) having been calculated are converted tothree-phase voltages (vu*, vv* vw*) based upon the rotational angle θ.Then, in step S811, the voltage commands are converted to pulse widths(tu, tv, tw) as expressed below based upon the DC input voltage vdc andthe PWM carrier cycle Tc.

tu=Tc·(1+vu*/vdc)/2

tv=Tc·(1+vv*/vdc)/2

tw=Tc·(1+vw*/vdc)/2  (2)

In step S812, the phase pulse widths corresponding to the individualphases are clamped so as to ensure that they do not deviate beyond a 0to Tc range. In more specific terms, a negative pulse width is correctedto 0 and any pulse width exceeding Tc is adjusted to Tc. Once the pulsewidths resulting from the adjustment are set in the PWM timers at themicrocomputer 39 in step S813, the processing ends and the operationreturns to the main processing, the flowchart of which is omitted in thedrawings.

Next, the overcurrent protection processing is described. First, inreference to the flowchart presented in FIG. 5, an overcurrent faultdetection executed in the related art is described. Following theprocessing start, the three-phase currents having been read in step S802in FIG. 4 are compared with a predetermined current level (thresholdvalue) in step S91. A current exceeding the predetermined level isjudged to be an overcurrent, and in this case, a counter C isincremented in step S92. If, on the other hand, the currents are equalto or less than the predetermined level, the counter is set to 0 in stepS93. In step S94, a decision is made as to whether or not the value atthe counter has reached a predetermined count value, and if it isdecided that the counter value exceeds the predetermined count value,all the transistor elements in the inverter are turned off in step S95,an overcurrent error flag is set in step S96 and then the operationreturns to the control processing flow in step S97. If the counter valueis equal to or less than the predetermined count value, the operationproceeds to step S97, and returns to the control processing. Once theovercurrent error flag is set, the processing in the flowchart presentedin FIG. 4 is suspended until the overcurrent error flag is cleared upondetermining that the processing can be restarted by following apredetermined procedure through separate processing (not shown). If noerror is detected, the inverter output currents are controlled throughthe processing sequence indicated in the flowchart presented in FIG. 4so as to achieve the predetermined command currents.

FIGS. 6A through 6D each present an example of a circuit state that maybe assumed in one of the fault modes, (1) output ground fault/powershort-circuit, (2) output line-to-line short-circuit and (3) outputphase-to-phase short-circuit, in which an overcurrent is likely to beinduced. It is to be noted that FIGS. 6A through 6D each show only apart of the inverter that is related to a given fault mode for purposesof simplification. While a fault may involve a plurality of locationsand a plurality of arms, an illustration of such a fault is omitted.

FIG. 6A shows a current flow induced by a ground fault occurring when atransistor located on the upper side of the U-phase arm is in the ONstate. An example of an output ground fault is described in furtherdetail below.

Output Ground Fault

FIG. 7A shows an output ground fault equivalent circuit. This equivalentcircuit is an LCR serial circuit constituted with a Y capacitor(assuming C1=C2), main capacitor C0, and a resistance 51(r) and aninductance 52(L) of a wiring between the ground and the ground faultpoint. Since the resistance value is small enough and C1 is sufficientlysmall compared to C0, a condition expressed as r²−4 L/C<0 exists andthus, a resonance current with a frequency fc, expressed in expression(3) below, flows through this serial circuit.

fc=(1/(L·2·C1)−(r/(2L))²)^(0.5)/2π[Hz]  (3)

The peak current ipeak may be expressed as;

ipeak=2V/((4L−r ²/(2·C1))^(0.5) [A]  (4)

with V representing the capacitor initial voltage. In this situation, ifthe inverter input DC voltage vdc is 350 [V] (the initial voltage V atC1 is half this value at 175 [V]), the resistance r of the wiring forone phase extending from the inverter to the motor is 1 [mΩ], itsinductance L is 0.5 [μH), the main capacitor C0=900 [μF] and the Ycapacitor=1 [μF], the frequency of the resonance current will be 159[kHz] and the peak current will be 495 [A].

Since the frequency of such an electric current is more than 10 timeshigher than the frequency of sampling executed at the microcomputercontrol frequency (=current detection frequency) through amicroprocessor (microcomputer)-based control method of the related art,it cannot be detected with ease via the microcomputer through thecontrol method of the related art. Furthermore, this current is lowerthan the overcurrent sensing level (600 [A] in the embodiment) set inconjunction with a typical protection circuit for the gate drivecircuit, and even if the transistors at the inverter are switched as thecurrent flows, the current path shown in FIG. 7B is altered to thecurrent path (see the arrows in the figure) in FIG. 7C. Thus, thetransitory phenomenon occurs at the equivalent circuit in FIG. 7A atevery switchover. As a result, the resonance current exceeding thecontinuous rating of, for instance, 300 [A], continuously flows.

The fault modes other than the ground fault mode include the powershort-circuit mode, line-to-line short-circuit mode and thephase-to-phase short-circuit mode. As FIGS. 6B, 6C and 6D indicate, thepath through which the short-circuit current flows and the operationexecuted in the power short-circuit mode, the line-to-line short-circuitmode and the phase-to-phase short-circuit mode are similar to oneanother. Since these modes are equivalent to the impedance betweeninverter output lines becoming lowered and the resonance frequenciescorresponding to the individual fault modes can be calculated throughsimilar operations, the line-to-line short-circuit mode is described insome detail below as a representative example.

Line-to-Line Short-Circuit

FIGS. 8A and 8B show how a current may flow in the line-to-lineshort-circuit mode shown in FIG. 6C. In the example presented in FIG. 8,line-to-line short-circuit occurs between the U-phase winding and theV-phase winding. It is to be noted that, for purposes of simplification,FIG. 8A only shows part of the inverter relevant to the particularline-to-line short-circuit event. Since the transistors related to theline-to-line short-circuit event may be anyone of the U-phasetransistors, the V-phase transistors or the W-phase transistors, thusthey are simply notated as SWa, SWb, Sp and Sn in the figure.

Assuming the capacitance of the main capacitor 12 as C0, the resistance53 and the inductance of the wiring between the short-circuited pointsrespectively as rs and Ls, the resonance frequency fcs can be calculatedas

fcs=(1/(Ls·C0)−(rs/(2Ls))²)^(0.5)/(2π)[Hz]  (5)

For instance, a resonance frequency value of 2.4 [kHz] can becalculated, applying the inductance Ls of 5 [μH] and the same circuitconstants as those described earlier. If the inverter PWM cycle is 10[kHz], the transistor SWa in FIG. 8A, for instance, is switched fourtimes during a single resonance cycle.

FIG. 9 schematically shows the current response that may be observedunder the conditions described above immediately after the short-circuitevent occurs. It is assumed that as the current response shown in thefigure occurs while the transistor Sp is in the ON state. The reasonthat the actual current waveforms in a period I and a period II differslightly each other, as shown in the figure, is as follows.

Period I: As the actual current overshoots by a significant extentrelative to the command current, though the current control is executed,the current continues to rise in the current, with the ON duty of thetransistor SWa shown in FIG. 8A being decreased. Since the inductance 54Ls is smaller than the motor winding inductance, the rate of change inthe electric current expressed as; di=v·dt/Ls (v is the voltage betweenshorted terminals) increases, which, in turn, induces an overshoot. Itis to be noted that the solid line arrows in FIG. 8A indicate the paththrough which the current flows while the transistor SWa is on (a DCvoltage is applied between the shorted lines), whereas the dotted linearrows in FIG. 8A indicate the path through which the electric currentflows while the transistor SWa is off (zero voltage is applied betweenthe shorted lines).

Time point ts: As the voltage command input to the coil (rs, Ls) isinverted to a negative value, the transistor SWb in FIG. 8B is selectedfor a switchover (on/off). The transistor Sn enters the ON state.

Period II: Since the inductance Ls at the coil is lower than normal,even if the duty of the transistor SWb shown in FIG. 8B is adjusted bycurrent control, the actual current largely undershoots compared withthe command current. It is to be noted that the solid line arrows inFIG. 8B indicate the path through which the current flows while thetransistor SWb is on (a DC voltage is applied between the shortedlines), whereas the dotted line arrows in FIG. 8B indicate the paththrough which the electric current flows while the transistor SWb is off(zero voltage is applied between the shorted lines).

The saw tooth waveform of the actual current shown in FIG. 9 may beinterpreted to indicate an oscillating control state, caused by arelatively high gain in the current control system according toimpedance decrease. In addition, the detection range of the currentdetectors used in the control is set up on the premise that the currentcontrol remains functional, as explained earlier. This means that, inthe event of a significant overshoot or undershoot, the detection valueswill be clamped, and that the control system will be further trappedinto the oscillation. Compared to the frequency of the current flowingin the ground fault mode, the frequency of the current flowing in theline-to-line short-circuit mode is lower and thus, the current can beaccurately sampled by the microcomputer within the detection range.Furthermore, any current that has been clamped can be recognized throughthis detection. However, there may still be situations in which anovercurrent cannot be detected based upon the overcurrent faultdetection algorithm normally used in the microcomputer.

overcurrent Fault Detection Method in the Related Art

The following is a description of the overcurrent fault detection methodin the related art, followed by descriptions of the overcurrent faultdetection device according to the present invention, which is improvedover the prior art, and of the detection method adopted in conjunctionwith the overcurrent fault detection device according to the presentinvention. In order to eliminate any risk of erroneous detection, a timewindow is set in an overcurrent fault detection algorithm normallyadopted in conjunction with a microcomputer. In more specific terms, ifan overcurrent is detected consecutively over a predetermined number ofsampling cycles, it is confirmed that an error has occurred in such anovercurrent fault detection algorithm (see the flowchart presented inFIG. 5).

However, an overcurrent may not be accurately recognized with theregular overcurrent fault detection algorithm adopted in conjunctionwith a microcomputer, as demonstrated in FIG. 10. In the example of FIG.10, it is assumed that current control and overcurrent fault detectionare carried out at 10 [kHz] in the system. This system is designed so asto determine that an overcurrent has occurred if an electric currentwith an oscillation frequency of 2.5 [kHz] and an amplitude of 450 [A]flows due to a line-to-line short-circuit fault and the current valueexceeds the threshold value over three consecutive sampling cycles setas the time window. FIG. 10 shows that a positive-side overcurrent isdetected twice consecutively and a negative-side overcurrent is alsodetected twice consecutively. However, since the overcurrent faultdetection criterion of an overcurrent, i.e. detection of overcurrentthree consecutive times, is not satisfied, it is not determined as anovercurrent has occurred. It is to be noted that overcurrent faultdetection points i1 and i2 on the positive side and overcurrent faultdetection points i4 and i5 on the negative side in FIG. 10 each indicatea point at which a clamped current value is detected.

If the system fails to recognize an overcurrent, as described above, itwill allow the oscillating current to flow continuously, which may leadto a fatal condition that will destroy the elements. In addition, in thetop fault mode, too, the impedance at the inverter output end willbecome very low and thus, the current control oscillation may beinduced.

Accordingly, the overcurrent fault detection device in the embodimentadopts an algorithm that allows an overcurrent to be accuratelyrecognized by detecting the frequency or the cycle of the high-frequencycurrent with a large amplitude induced in any of the three fault modesdescribed earlier. Namely, in addition to the algorithm for recognizingan overcurrent when the current amplitude exceeds a predeterminedthreshold value, a frequency/cycle detection algorithm is also builtinto the overcurrent fault detection device in the embodiment.

The following is a description of the overcurrent fault detection deviceand the overcurrent fault detection method according to the presentinvention.

Embodiment 1

As has already been described in reference to FIG. 3, the outputs of theindividual phase current detectors are input to the A/D converter 19 inthe microcomputer 39 and are also input to the comparator withhysteresis 20. In order to convert the current oscillating with largeamplitude into pulses, the hysteresis width may be set, for example, toapproximately 100 [A] for the comparator with hysteresis 20, whentransistors with a continuous rating of 300 [A] are used. The output ofthe comparator 20 is connected to terminals at the external pulsecounters 21, 22 and 23 in the microcomputer 39. Initial settings aredone through separate processing (not shown) for the pulse counters 21,22 and 23 so that a count increment occurs at the leading edge of apulse.

In addition, for controlling the electric current and the torque at themotor 3, the output of the DC voltage detector 4 is input to the A/Dconverter 19, and the R/D converter 24 that converts the signal from therotational position detector (resolver) 8 into an angle is connected tothe external bus 25 of the microcomputer 39. At each PWM timer (26, 27or 28) in the microcomputer 39, the ON time, i.e., the length of timeover which the transistors in the corresponding phase constituting theinverter 2 switched to ON state, is set, and the microcomputer 39outputs a PWM signal to the gate drive circuit 10. The ON time of thetransistors corresponding to each phase is determined through anarithmetic operation executed by the CPU 31. A common carrier (fc) timer29 is connected to the PWM timers 26, 27 and 28 corresponding to theindividual phases and thus, a PWM carrier cycle in each phase isgenerated with the carrier timer. Then, a narrow pulse (e.g., a pulse“1” with a width 1 [μs]) is output over each carrier cycle, and theconversion via the A/D converter 19 is started and the various phasecurrents (iu, iv, iw) and the DC voltage vdc, which are sampled bysequentially switching their inputs via the multiplexer & sample hold 32(sampling circuit), are stored into the corresponding resistors asinitial settings in a separate processing (not shown in the figure).

Overcurrent Fault Detection Processing

FIG. 11 presents a flowchart of the overcurrent fault detectionprocessing according to the present invention. The processing in thisflowchart is executed over predetermined cycles. The overcurrent faultdetection processing is called up in step S805 in FIG. 4 each time thecurrent control processing is executed in the embodiment. First, throughthe processing executed in step S501 through step S504 in the flowchartpresented in FIG. 11, a decision as to whether or not an overcurrent hasoccurred is made by comparing the amplitudes of the currents with thethreshold value. Then, in step S505, a counter value Fk is read fromeach external pulse counter to which the comparator with hysteresis isconnected. Upon completing the read, the counter is cleared in stepS506.

Assuming that the processing is executed every 100 [μs] (i.e. every timethe current control processing is executed over 100 [μs] cycles), an Fkvalue of 1 will be equivalent to 1/100 [μs]=10 [kHz]. Namely, the pulsefrequency FPk [Hz] can be converted to a frequency as expressed;

FPk=Fk/Tsampl  (6)

with Tsampl [s] representing the processing execution cycle. Inaddition, a counter threshold value Flimit in reference to whichovercurrent decision-making is executed may be set as;

Flimit=FPlimit·Tsampl  (7)

with FPlimit [Hz] representing the frequency threshold value.

In step S507, the counter value Fk is compared with the threshold valueFlimit of the counter for determining that an overcurrent has occurred.If the counter value exceeds the threshold value, all the transistorelements in the inverter are turned off in step S508, an overcurrenterror flag is set in step S509 and then the operation returns to thecurrent control processing in step S510. Once the overcurrent error flagis set, the processing in the flowchart presented in FIG. 4 is suspendeduntil the overcurrent error flag is cleared upon deciding that theprocessing can be restarted by following a predetermined procedurethrough separate processing (not shown).

It is to be noted that in the event of a fault occurring in a fault modesuch as the line-to-line short-circuit mode, the frequency of theoscillating overcurrent may be lower than the current control cycle and,in such a case, the processing in step S505 through step S509 may beexecuted over a cycle different from the current control cycle, e.g.,the processing may be executed every 10 [ms].

Assuming the capacitance of the Y capacitor in an inverter typicallyutilized in automotive applications to be equal to or less than 2 [μF],and the length of the wiring extending from the inverter to the motor tobe equal to or less that 10 [m], whereby the resistance and theinductance at the wiring are respectively 1 [mΩ] or less and 1 [μH] orless and that a ground fault has occurred at a wiring end, the resonancefrequency is calculated to be 113 [Hz] through expression (3). 113 [Hz]thus calculated can be set as FPlimit.

In addition, when a line-to-line short-circuit detection or aphase-to-phase short-circuit detection is carried out, the settings forthese detections are done in reference to the current control cycle(current detection cycle) of the microcomputer. For instance, when thecurrents are detected every 100 [μs], assuming that the microcomputerwill not be able to complete the overcurrent decision-making based uponthe detected currents within a length of time 10 times the length of thecurrent detection cycle, 1 [kHz] may be set for FPlimit. This FPlimitvalue is lower than the frequency measured in the event of a groundfault, overcurrent faults including the ground fault can be detected.

It is to be noted that the frequency of an overcurrent occurring in theground fault mode, the line-to-line short-circuit mode or thephase-to-phase short-circuit mode can be calculated as expressed in (3)or (5). However, since a relationship expressed as; 1/(L·2·C1)>>(r/(2L))² or 1/(Ls·C0)>>(rs/(2 Ls))² is satisfied in the correspondingexpression in these fault modes, the expressions can be simplified to;

fc=(1/(L·2·C1))^(0.5)/(2π)[Hz]  (8)

or

fcs=(1/(Ls·C0))^(0.5)/(2π)[Hz]  (9)

The frequency can thus be calculated as expressed in (8) or (9).

However, in a motor drive system that drives a motor with eight pairs ofpoles at a maximum rotation rate of 10,000 [rpm], the frequency of afundamental current output from the inverter will be as high as 1.333[kHz] (=(10,000/60)×8), which may lead to a trouble of erroneousovercurrent detection, even though this is a normal operation condition,when a comparator having a hysteresis width centered at 0 is used.

In order to prevent such trouble, a comparator assuming a hysteresiswidth centered on the inverter fundamental current may be employed. Forinstance, a type 2 (see FIG. 16B) comparator with hysteresis equippedwith a hysteresis central value altering circuit may be utilized. Aspecific method of detection executed in conjunction with such acomparator will be described later in reference to embodiment 3. As analternative, a type 3 (see FIG. 16C) comparator with hysteresis equippedwith a subtractor circuit may be utilized.

Embodiment 2

FIG. 12 is a block diagram of the control circuit achieved in anotherembodiment of the present invention. This control circuit ischaracterized in that; replacing the counters 21, 22 and 23 in themicrocomputer with (1) the comparator outputs corresponding to thevarious phases are each connected to a terminal of one of three captures34, 35 and 36, (2) an additional free-run counter 37 installed forpurposes of time count, and (3) a DMA controller 38 is added in order totransfer data output from the individual captures to predetermined RAMareas.

As shown in FIG. 13A, each capture reads the values indicated at thefree-run counter 37 at the rising edge and the falling edge (two edges)of a pulse input to a terminal thereof and transfers the values thusread to a specifide register. In response to the two edges of the pulse,the DMA controller 38 sequentially transfers the register values to apredetermined RAM address. Each time the DMA controller 38 transfersdata, it increments the address by n [bytes]. Once it reaches aspecifide stop address, the address is initialized to the start addressand the DMA controller continuously increments the address each time ittransfers data.

In the example presented in FIG. 13B, each register holds four bytes ofdata and the DMA controller is set so that each time a total of foursets of data (16 [bytes]) is transferred to the RAM, the DMA destinationaddress is initialized to the start address (from address “3” to address“0” in the figure).

FIG. 14 presents a flowchart of the overcurrent fault detectionprocessing executed in the embodiment. This processing is executed witha predetermined cycle, e.g., 10 [ms], which is different from thecurrent control cycle. After the processing start, the current detectionvalues are captured and the count values at the free-run counter 37,stored in a predetermined area in the RAM, are read in step S601. Atthis time, two sets of data (Ak(n), Ak(n+1)) are read from two adjacentaddresses. More specifically, data are read cyclically two sets at atime, e.g., data from address 0 and address 1, data from address 1 andaddress 2, data from address 2 and address 3, data from address 3 andaddress 0, data from address 0 and address 1, and so forth.

In step S602, the difference (pulse cycle) between the two sets of datais calculated. While the flowchart does not include details, the datafrom the end point address are subtracted from the data from the startpoint address if the two sets of data have been read from the startpoint address and the end point address, but otherwise the data of theaddress with the smaller address number are subtracted from the data ofthe address with the larger address number in this step. In other words,the data having been captured earlier are subtracted from the datacaptured later. Through this operation, the positions of risingedge/falling edge of the pulse are detected, and the frequency of thepulse can then be determined based upon the positions of risingedge/falling edge of the pulse.

In step S603, the pulse cycle having been measured is compared with thethreshold value so as to determine whether or not an overcurrent hasoccurred. If the cycle is less than a predetermined level, it isdetermined that an overcurrent has occurred. In this case, all thetransistor elements in the inverter 2 are turned off in step S604, anovercurrent error flag is set in step S605, and then the operationreturns to the current control processing in step S606. If the cycle isequal to or greater than the predetermined value, the operation proceedsto step S606 to return to the current control processing. It is to benoted that settings should be selected so as to call up the overcurrentfault detection processing, executed as shown in the flowchart presentedin FIG. 5 by detecting the amplitudes through the method in the relatedart, in step S805 in the current control processing flowchart presentedin FIG. 4.

The devices achieved in embodiments 1 and 2 each achieve a uniqueadvantage in that since a decision as to whether or not an overcurrenthas occurred is made based upon the frequency or the cycle, anovercurrent can be detected even when the peak of the high-frequencycurrent is beyond the detection range of the current detectors connectedto the control microcomputer or when true current values cannot be readdue to clamping.

The cycle length threshold value, in reference to which such a decisionis made, may be set to the reciprocal of the frequency threshold valueby which the decision is made in the method described in reference toembodiment 1.

FIG. 15 shows the functional blocks corresponding to one phase, whichare involved in the overcurrent fault detection processing executed inembodiment 1 or embodiment 2. Both the embodiment 1 and embodiment 2 areprovided with an overcurrent fault detection unit that detects anovercurrent based upon the current frequency or the current cycle, inaddition to an overcurrent fault detection unit that detects anovercurrent based upon the current amplitude. In either embodiment, thecontrol circuit generates an overcurrent fault detection signal basedupon the OR of the outputs from the two detection units, and thus, anabnormal current caused by a ground fault, phase-to-phase short-circuitor line-to-line short-circuit, which cannot be detected easily in therelated art, can be detected.

Embodiment 3

FIGS. 16A through 16C each present an example of a structure ofcomparator with hysteresis used in the present invention for one phase.Each comparator with hysteresis operates in conjunction with a currentdetector having an output range of 0 to 5 [V], which outputs 2.5 [V]when the current value is 0 [A]. For purposes of convenience, thefollowing description is provided by assuming that the voltage is outputlinearly relative to the current, with 5 [V] output at 300 [A] and 0 [V]output at −300 [A].

The type 1 comparator with hysteresis shown in FIG. 16A is an opencollector output-type comparator that can be driven on a single 5 [V]power source and comprises R1 to R3 used to form a hysteretic voltage(width) and a pull-up resistor Rp used on the comparator output side.Assuming that R1=R2=R3 and Rp is sufficiently smaller than R1, and thatV is 5 [V], the hysteresis width of the comparator becomes ±0.84 [V]centered on 2.5 [V]. The threshold based upon the characteristics of thecurrent detector described above is ±100 [A] (=0.84×300/2.5) and thus,the comparator outputs will indicate “0” when the current exceeds 100[A] and the comparator output will switch to “1” when the currentbecomes lower than −100 [A].

For instance, in the event of a ground fault or line-to-lineshort-circuit as described earlier, a oscillating current exceeding 400[A] flows. Thus, the comparator output is provided as a 159 [kHz] pulsetrain in the event of a ground fault, whereas the comparator output isprovided as a 2.5 [kHz] pulse train in the event of line-to-lineshort-circuit. The decision as to whether or not an overcurrent hasoccurred can be made through the microcomputer processing described inreference to embodiment 1 or embodiment 2. In addition, the cause of anovercurrent can be identified as a ground fault or as line-to-lineshort-circuit based upon the pulse frequency, as described later.

Namely, a specific fault mode among the fault modes described earliercan be identified.

Unlike the type 1 comparator with hysteresis provided with thecomparison reference voltage V(fixed), the type 2 comparator withhysteresis in FIG. 16B uses a detected phase current value held withpredetermined timing. It is to be noted that a diode D and a resistorRpo (Rpo<<Rp) added at the comparator output are used to convert theoutput voltage to 0-5 [V]. The comparator with hysteresis adopting thissystem assumes a hysteresis width centered on the actual currentdetected at the particular sampling point.

FIG. 17 presents an example of a waveform with a beat-like oscillatingcurrent superposed on a sine-wave-like low-frequency current(corresponds to the command current). This kind of waveform may begenerated in the event of line-to-line short-circuit or phase-to-phaseshort-circuit shown in FIG. 6C or FIG. 6D. For this kind of waveform, orfor the case that the fundamental wave frequency is close to thefrequency induced by oscillation, the type 2 comparator with hysteresisshown in FIG. 16B is particularly effective.

As shown in FIG. 16B, holding of the current value can be performed by asample hold circuit constituted with a buffer operational amplifier 40,a capacitor Cs and an analog switch. As the analog switch closes at thehold timing, and the capacitor is charged with the voltage of the holdtiming. Subsequently, the analog switch opens, and the voltageimmediately before the switch is opened (i.e., the detected currentvalue) is held.

It is to be noted that the hysteresis central value can be adjusted byproviding an output Vr of a hysteresis central value altering circuit,constituted with the sample hold circuit described above, a resistor R4and diodes D1 and D2 to the comparator instead of the voltage V providedto the type 1 comparator with hysteresis.

The type 3 comparator with hysteresis shown in FIG. 16C, althoughassuming a more complicated circuit structure than the type 2 comparatoris, nevertheless, similar to the type 2 comparator with hysteresis inthat it compares the detection value to a reference value centered onthe actual current held with predetermined timing. While the comparatorwith hysteresis itself in this circuit structure is identical to thetype 1 comparator, the circuit includes a differential amplifierconstituted with operational amplifiers 40, 41 and 42 and resistors R11through R14, which is engaged in comparator preprocessing through whichthe actual current held with the predetermined timing is subtracted fromthe detected current. Thus, it achieves a unique advantage in that thehysteresis width does not change, which the type 2 comparator withhysteresis does not provide, while proving to be particularly effective,as is the type 2 comparator with hysteresis when a beat-like oscillatingcurrent centered on a low-frequency current (command current) appears orwhen the fundamental frequency is close to the frequency induced byoscillation.

The predetermined timing with which the current value is held at thetype 2 comparator with hysteresis and the type 3 comparator withhysteresis may be, for instance, set in correspondence to the PWMcarrier cycle. Such timing may be set by the microcomputer 39, asindicated in the block diagram provided in FIG. 3 or FIG. 12.

As a variation to the type 2 comparator with hysteresis or the type 3comparator with hysteresis, a voltage value corresponding to the commandcurrent value, in place of the actual current value held at apredetermined timing, may be output from the microcomputer 39 via, forinstance, a D/A converter, and the voltage value thus output may be usedas the comparison reference voltage at the comparator. As a furtheralternative, the results obtained by subtracting the voltage valuecorresponding to the command current value from a voltage value thatcorresponds to the actual current value may be provided to a comparatorwith a fixed hysteresis width.

While all the transistors in the inverter are turned off through themicrocomputer processing in the embodiments described above, a circuitsuch as that shown in FIG. 18 may be built into the gate drive circuitso as to turn off all the transistors in response to decision results bythe microcomputer 39. The circuit shown in FIG. 18 corresponds to onephase of PWM signals. The overcurrent fault signal is designed so as toindicate “1” upon detecting an abnormal current but indicate “0”otherwise. All the transistors in the inverter can be turned off bydesigning the gate drive circuit so as to turn off the transistors inresponse to the overcurrent fault signal indicating “1”.

While the transistors in the inverter are all turned off as a protectivemeasure upon determining that a fault has occurred, all the upper armtransistors or all the lower arm transistors in the inverter may beturned on as an alternative. In such a case, an open state is assumedbetween the DC power source (battery) and the load and thus, all theload terminals become shorted.

In addition, the cause of an overcurrent fault can be determined and thecorresponding fault mode can be identified by adopting the algorithm inthe flowchart presented in FIG. 19. The processing executed as shown inthe flowchart presented in FIG. 19 is described below. In step S191, thefrequency having been stored into a specifide RAM address through theprocessing shown in FIG. 11 is input. The value input in this step isobtained by converting the counter FK value to a frequency. Next, instep S192, a decision is made as to whether or not the frequency havingbeen input is equal to or greater than 100 kHz, and if an affirmativedecision is made, the fault mode is determined to be the ground faultmode in step S194, and the operation returns in step S195. If, on theother hand, a negative decision is made, the fault mode is judged to beeither the phase-to-phase short-circuit mode or the line-to-lineshort-circuit mode in step S193, and returns in step S195. By storingthe fault mode thus identified into a nonvolatile memory or the like,these data can be read out later and utilized for determination offailure location.

While the overcurrent fault detection algorithm described enablesdetection of an overcurrent based upon the frequency, a similaralgorithm may be adopted in the cycle length based overcurrentdecision-making shown in FIG. 14. In such a case, additional processingmust be executed to convert the cycle (Pk) to a frequency value whenreading data in step S191.

While the two overcurrent fault detection algorithms, i.e., the currentamplitude value based overcurrent fault detection algorithm and thecurrent frequency/cycle based overcurrent fault detection algorithm, arebuilt into the control system in the examples described above, thepresent invention may also be adopted in an overcurrent fault detectiondevice equipped with only the current frequency based overcurrent faultdetection algorithm or with only the current cycle based overcurrentfault detection algorithm.

By adopting the overcurrent fault detection device and the overcurrentfault detection method according to the present invention describedabove, an error caused by an output ground fault/power short-circuit,output line-to-line short-circuit or output phase-to-phase short-circuitin an electrical drive control system, which cannot easily be detectedthrough sampling via a microcomputer typically engaged in the invertercontrol of the related art, can be detected with a higher level ofreliability and with greater ease.

The various embodiments described above may be used either singly or incombination. This is because the beneficial effects of each of theembodiments may be obtained either singly or in synergy. Moreover,provided that the essential characteristics of the present invention arenot lost, the present invention is not to be considered as being limitedby any of the embodiments described above.

It is to be noted that while overcurrent detection executed in anelectrical drive control system is described above, the presentinvention may be also adopted in detection of a oscillating current,which may not necessarily be an overcurrent, occurring in an electricaldrive control system. In addition, while an explanation has been givenabove in reference to examples in which the present invention is adoptedin the inverter in a hybrid drive vehicle or an electric vehicle, thepresent invention may be adopted in applications other than applicationspertaining to these particular types of vehicles. In other words, thepresent invention may be adopted in various types of equipment andvehicles including railway vehicles, industrial vehicles andconstruction machines. Furthermore, the present invention may be adoptedin all types of inverters used in industrial applications and homeappliance applications.

What is claimed is:
 1. An overcurrent fault detection device,comprising: an inverter that converts a DC current to three-phase ACcurrents in order to drive a motor; a DC voltage detector that detects aDC voltage value of a DC voltage flowing to the inverter; phase currentdetectors that detect respective phase current values of the three-phaseAC currents; a rotational position detector that detects a rotationalangle of the motor; a control circuit that controls a gate drivecircuit, which controls output currents of the inverter at everypredetermined cycle, based upon the phase current values provided by thephase current detectors, a motor rotational angle detection valueprovided by the rotational position detector and a speed command or atorque command issued by a higher-order control device; and adecision-making circuit that detects an overcurrent based upon the phasecurrent values detected by the phase current detectors at everypredetermined cycle, wherein: the decision-making circuit determineswhether or not the phase current values exceed a predetermined amplitudethreshold value by carrying out frequency detection for any of the phasecurrent values exceeding the predetermined amplitude threshold value,and determines that an overcurrent has occurred upon detecting thefrequency; and the decision-making circuit includes a comparator withhysteresis provided with a predetermined hysteresis width, which carriesout the frequency detection for any of the phase current values; theovercurrent fault detection device further comprising: a capture thatdetects a rising edge position and a falling edge position of a pulseoutput from the comparator with hysteresis; and a free-run counter,wherein: the decision-making circuit detects that a cycle length of anyof the phase current values exceeding a predetermined amplitude basedupon the rising edge position and the falling edge position of thepulse, and detects a frequency of any of the phase current valuesexceeding the predetermined amplitude based upon the cycle length.
 2. Anovercurrent fault detection device according to claim 1, wherein thedecision-making circuit detects an overcurrent in the everypredetermined cycle; and the decision-making circuit determines that anovercurrent has occurred if any of the phase current values detected bythe phase current detectors exceeds a predetermined amplitude thresholdvalue.
 3. An overcurrent fault detection device according to claim 1,wherein: the decision-making circuit further includes a hysteresiscentral value altering circuit that adjusts a hysteresis center assumedby the comparator with hysteresis in correspondence to a predeterminedcurrent value.
 4. An overcurrent fault detection device according toclaim 1, wherein: the decision-making circuit further includes asubtractor circuit that subtracts a predetermined current value from anyof the phase current values and inputs subtraction results; and anoutput from the subtractor circuit is input to the comparator withhysteresis.
 5. An overcurrent fault detection device according to claim3, wherein: the decision-making circuit further includes a sample hold;and any of the phase current values held by the sample hold at apredetermined time interval is used as the predetermined current value.6. An overcurrent fault detection device according to claim 3, wherein:a command current value is used as the predetermined current value. 7.An overcurrent fault detection device according to claim 1, furthercomprising: counters that count numbers of times of exceeding apredetermined amplitude for the phase current values respectively, bycounting changes in output from the comparator with hysteresis, wherein:the decision-making circuit determines that an overcurrent has occurredupon detecting that any of the phase current values takes on a frequencyof which amplitude exceeds a predetermined amplitude, based upon a countvalue having been counted on the counters.
 8. An overcurrent faultdetection device according to claim 1, wherein: a cause of anovercurrent fault occurring in an electrical drive control system isdetermined, based upon a frequency of any of the phase current valuesexceeding the predetermined amplitude, which is detected by thedecision-making circuit.
 9. An overcurrent fault detection deviceaccording to claim 1, wherein: gate signals for transistors at theinverter are turned off so as to protect the transistors upondetermining that an overcurrent has occurred.